The GX2482e is a PXI express compatible, dual-channel, 16-bit digitizer. [1] It offers a high dynamic range and excellent SFDR. [1] It is suitable for applications such as aerospace, defense, automotive testing, high-performance baseband testing, medical device and module testing, and ATE systems. [1]
Here are some of its features:
Inputs: It has two differential inputs that can also be configured for single-ended operation. [1]
Input Impedance: Selectable for 1M ohm or 50 ohms and can be AC or DC coupled. [1]
Resolution: 16-bit. [1]
Sample Rate: Up to 180 MS/s. [1] The sample rate can be programmed from 1 MHz to 180 MHz. [1]
Memory: 64 M Sample memory depth per channel. [1]
Low Pass Filters: Each channel offers 3 selectable low pass filters. [1]
Clocking: It has a PLL clock generator with dedicated clock dividers for each channel, providing independent clocking and flexibility. [1]
Input range: 0.256 Vp to 15.36 Vp [1]
External Clock: The external clock connector is a front panel SMB with a 50 Ohm nominal input impedance. [1] The input frequency range is DC to 945 MHz for direct clocking, or 10 MHz as PLL reference. [1] The threshold level is 1.02 V, ±5% with a hysteresis of 60 mV, typical. [1]
Triggering: Triggering sources include the front panel, PXI trigger 0-7, PXI Star trigger, software trigger, and input signal. [1] Triggering modes are positive/negative level or edge, and positive/negative edge continuous. [1]
General specifications include:
Size: 3U, single slot. [1]
Weight: Approximately 0.55 lbs. [1]
Operating Temperature: 0 °C to +50 °C. [1]
Storage Temperature: 0 °C to +70 °C. [1]
Humidity: 10% to 80% (Non-Condensing). [1]
Current Consumption (Maximum): +5 V @ 2.3 A, +12 V @ 10 mA, -12 V @ 110 mA, +3.3 V @ 1.8 A. [1]
Accessories include:
GX92104 SMB Plug to BNC-M Cable, 36 inches (RG188 Cable). [1]GX92105 Dual SMB to BNC Cable, 12 inches. [1]GX92106 SMB Plug to SMA-M Cable, 24 inches (RG188 Cable). [1]
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- PXIe FPGA Digital I/O Board - GX3700e | Marvin Test Solutions, Inc.
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FEATURES The GX2482 provides two, differential inputs offering the ability to make low level measurements in the presence of common mode or noisy signals. The inputs can also be configured for single-ended operation. The input impedance is selectable for 1M oh...
Results from Downloads GX2482DS.pdf Feb 21, 2023 version: A 226.65 KB GX2482 Data Sheet type: Datasheet GX2482xUG.pdf May 1, 2020 version: 1 1.43 MB GX2482/GX2482e User's Guide type: Manual GX2482_pa72.exe May 24, 2016 version: 1.2 13.11 MB GX2482 Driver t...
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Supports up to 875 Mbps receive and 840 Mbps transmit LVDS communications data rates. Support for Bus LVDS (BLVDS), LVDS, RSDS®, mini-LVDS and PPDS® differential I/O standards. Supported I/O standards include LVTTL, LVCMOS, SSTL, HSTL, PCI, PCI-X, LVPECL, LVDS...
Comments When programmed by a call to Gx3722HighBandwidthSetFrequency() API, the specified channel will output a square wave: a pulse train with a fixed duty cycle of 50%. This function can be used to retrieve the frequency selection of an actively outputting ...
Type 2 receiver Data Rate 200 Mbps (max) Differential Output Voltage 480 mV (min), 650 mV (max) Differential Input Voltage Threshold 150 mV (max) (positive going input) 50 mV (max) (negative going input) Absolute Maximum Input Voltage Range -1.8 V to 4 V Power...
If no signal is detected after 100 millseconds of calling this function, pnMeasurementStatus will be assigned the value of and the values of pdFrequency and pdPulseWidth will be invalid. Example The following example performs a measurement from High Bandwidth ...
Applications Automatic Test Equipment (ATE) Semiconductor test Custom interface emulation Custom instrumentation SerDes interfaces GX3700e Specifications External Digital I/O Channels Logic Families LVTTL, LVDS, configurable for 1.2 / 2.5 / 3.3 V logic; 5 V co...
Applications Automatic Test Equipment (ATE) Semiconductor test Custom interface emulation Custom instrumentation SerDes interfaces GX3700e Specifications External Digital I/O Channels Logic Families LVTTL, LVDS, configurable for 1.2 / 2.5 / 3.3 V logic; 5 V co...
Threshold Accuracy ± 1% . Comparator Response Time 1uS max. Voltage Measurement All channels - 0 to 48V with 12mV resolution. Voltage Measurement Accuracy ± 1% of measured value. Environmental Operating Temperature 0 °C to +50 °C. Storage Temperature -20 °C to...
Applications Automatic Test Equipment (ATE) Semiconductor test Custom interface emulation Custom instrumentation SerDes interfaces GX3700e Specifications External Digital I/O Channels Logic Families LVTTL, LVDS, configurable for 1.2 / 2.5 / 3.3 V logic; 5 V co...
There are 56 Digital I/O channels, channel's direction control is set in groups of 4 channels, eg channels 0-3, channels 4-7, etc. Any group of channels can be programmed to be all in or all out.
There are 56 Digital I/O channels, channel's direction control is set in groups of 4 channels, eg channels 0-3, channels 4-7, etc. Any group of channels can be programmed to be all in or all out.
Programming and Software The board is supplied with the GxFPGA library, a software package that includes a virtual instrument panel, and a Windows 32/64-bit DLL driver library and documentation.
The signals are 5 V tolerant. Logic families supported by the I/O interface include LVTTL and LVCMOS. The FPGA device supports up to four phase lock loops for clock synthesis, clock generation and for support of the I/O interface.
There are 56 Digital I/O channels, channel's direction control is set in groups of 4 channels, eg channels 0-3, channels 4-7, etc. Any group of channels can be programmed to be all in or all out.
Direction is configurable by software on a per pin basis Logic Family Differential TTL, RS-422 & RS-485 compatible Data Rate 100 Mbps (max) Driver Output Current ±60 mA (sink or source) (max) Differential Output Voltage 1.5 V (min), 6 V (max) (no load) Rec...
The signals are 5 V tolerant. Logic families supported by the I/O interface include LVTTL and LVCMOS. The FPGA device supports up to four phase lock loops for clock synthesis, clock generation and for support of the I/O interface.
Programming and Software The board is supplied with the GxFPGA library, a software package that includes a virtual instrument panel, and a Windows 32/64-bit DLL driver library and documentation.
The signals are 5 V tolerant. Logic families supported by the I/O interface include LVTTL and LVCMOS. The FPGA device supports up to four phase lock loops for clock synthesis, clock generation and for support of the I/O interface.
The signals are 5 V tolerant. Logic families supported by the I/O interface include LVTTL and LVCMOS. The FPGA device supports up to four phase lock loops for clock synthesis, clock generation and for support of the I/O interface.
The signals are 5 V tolerant. Logic families supported by the I/O interface include LVTTL and LVCMOS. The FPGA device supports up to four phase lock loops for clock synthesis, clock generation and for support of the I/O interface.
An on-board 80 MHz oscillator is available for use with the FGPA device or alternatively, the PXI 10 MHz clock can be used as a clock reference by the FPGA.
The signals are 5 V tolerant. Logic families supported by the I/O interface include LVTTL and LVCMOS. The FPGA device supports up to four phase lock loops for clock synthesis, clock generation and for support of the I/O interface.