Architecture
ROM Emulation is a powerful and versatile method of microprocessor testing. ROM emulation has emerged as the technique of choice for microprocessor test and diagnostic applications. A microprocessor-based board is tested by replacing the boot ROMs on the Unit Under Test (UUT) with memory emulation pods. Each pod handles 8 bits of the data bus. Processors from 8 to 32 bits can be controlled with 1 to 4 pods (even the most advanced CPUs such as the Intel Pentium generally use only an 8-bit boot path). The emulator takes control of the UUT by re-setting the processor and under the test program's control (monitor program) exercises all functions on the board. Synchronization with the UUT is automatic and requires no additional hardware or connections.
Configuration
ROM emulation uses a high level language that enables the user to focus on development of the test procedure (rather than on learning new opcodes of the tested CPU) allowing rapid transition from one test program development to another with minimum learning time. The controlling link is transparent to the user.
Programming and Software
The board is supplied with a 32-bit DLL driver. Various interface files provide access to the DLL from programming tools and languages such as ATEasy, LabVIEW, C/C++, Microsoft Visual Basic®, Delphi, and more. The available virtual panel can be used to interactively monitor and control the instrument from a window that displays the instrument's current settings and measurements.
On-Line help file and PDF User's Guide provides documentation that includes instructions for installing, using and programming the board.
Applications
- Automated Test Equipment (ATE)
- Workstation Service and Repair
- Engineering Evaluation
- Microprocessor Board Emulation
NT5000-5100 Series Specifications
| General |
|---|
| Boot ROM Path | 8 and 16 bits (NT5000)
8, 16, and 32 bits (NT5100) |
| Number of PC Slots | 1 (NT5000)
2 (NT5100) |
| Trigger Bus |
|---|
| Output | Breakpoint, SW Out
User Trigger
R/W Trigger
UUT Trigger
Reset Trigger |
| Input | GP-In1, GP-In2 status |
| Supported ROM Types |
|---|
| Size | 64 Kb to 8 Mb |
| Package | 28 or 32 pin DIP or PLCC.
Other styles available by special request |
| Access Time | 55 ns or less |
| Stimuli Output |
|---|
| Software Controlled Signals | Sourcing or sinking 60 mA |
| Reset Overdrive line | Drive Current 64 mA |
| Level | Software selectable high and low pulse |
| Pulse Width | 1 ms to 10 s |
| Microprocessor Emulation Speed | Maximum rated execution speed with no wait status |
| Pod Signal Loading | 100 Ω |
| Pod Cable Lengths | PC to Pod: 6 feet
Pod to ROM Socket: 1 foot |
| Number of General Purpose I/O Pins | 16 bits of general-purpose I/O lines; each line can be configured as input or output. |
| Connections | Two 50-pin high density connectors support two 8-bit pods or one 16-bit pod |
| System Requirements |
|---|
| Hardware | 486DX 33 MHz or higher |
| Memory | 4 MB memory, 2 MB hard disk space, VGA monitor, mouse, and one 16-bit ISA slot |
| Software | DOS Ver 5.0 and Windows 3.1 or higher |
Note: Specifications are subject to change without notice.
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