Test Connections - November 2016

Using IEEE 1149.1-2013 (JTAG) with ATEasy®


ATEasy is a flexible integrated Test Executive development environment for board and system-level test. Intellitech’s NEBULA software provides an important bridge from ATEasy to JTAG accessible on-chip instruments when a non-intrusive method of test is required.  The user can compile IEEE 1149.1-2013 instrument descriptions and operational libraries in PDL within Intellitech’s NEBULA or Eclipse™ software and then access these procedures from ATEasy.

On-chip instruments are as useful as external GPIB/PXI/VXI/LXI based instruments and have the advantage over those instruments in that they don’t require physical access.

Using JTAG with ATEasy

IEEE 1149.1-2013 added substantially to the original IEEE 1149.1-2001 standard for supporting test structures inside the IC.  It includes definitions of hierarchically-accessible Intellectual Property (IP) blocks, standalone descriptions of IP block functions, and support for a standardized procedural language which allows communication to all things in the silicon via the Test Access Port (TAP).

When integrated with boundary-scan tools to read values such as temperature and on-board voltages, ATEasy can be used to support JTAG/IEEE 1149.1 based instrument control, programming and test.  Overall test program flow and control is basically the same for the older boundary-scan interconnect tests or FPGA programming via JTAG as it is for the new on-chip register support.

By incorporating tools such as NEBULA with ATEasy, board and system test engineers have additional test capabilities that offer robust and non-contact test capabilities.

To learn more about how to use IEEE 1149.1-2013 (JTAG) with ATEasy, please register to download: Using IEEE 1149.1-2013 (JTAG) with ATEasy.